Advanced FPGA Engineer

Bachelor's degree in Electrical or Computer Engineering, or a related Science, Engineering or Mathematics field, plus a minimum of 5 years of relevant experience; or Master's degree plus a minimum of 3 years of relevant experience.

CLEARANCE REQUIREMENTS: Ability to obtain a Department of Defense TS/SCI security clearance is required at time of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required.

Role and Position Objectives:

As an FPGA design engineer, you'll be a member of a cross functional team responsible for product design from system architecture & requirements allocation through product release and production of cost-sensitive secure products.

We encourage you to apply if you have any of these preferred skills or experiences: Experience with VHDL/Verilog/SystemVerilog and TCL or similar languages, Zync UltraScale+ MPSoC or similar FPGAs, Vivado or similar tools.

The ideal candidate will be able to work independently to determine approaches to challenges, and may provide leadership and direction to less experienced team members.

Knowledge, Skills and Abilities:
* Proficient in the principles and techniques of FPGA design. Keeps abreast of technology trends.
* Proficient written and verbal communications skills,aAbility to think creatively, and multi-task.
* Proficient skill in communicating issues, impacts, and corrective actions.
* Works under limited direction. Regular contact with senior levels of internal work groups. Contact with project leaders and other professionals within the Engineering department and with project teams across the company. Some contact with external customers.

What Sets You Apart:

* Experience with Zynq processors using Petalinux, Yocto, or Buildroot.

* Experience with Git for version control and CI/CD flows for FPGA.

* Experience with Multi-Gigabit Transceivers (MGTs): GTX/GTH/GTY/GTZ/etc...

* Experience with bus protocols like: 1G/10G/40G/100+G Ethernet, Interlaken, Aurora/SerialLite II, RS-232, SPI, I2C, and CAN.

* Experience interfacing to external memory interfaces like: DRAM / SRAM.

* Understanding of static timing analysis, timing closure and floor planning techniques for designs that include but are not limited to custom developed solutions with embedded hard & soft processors and with commercial & custom IP.

Target salary range: USD $125,738.00/Yr. - USD $134,000.00/Yr. This estimate represents the typical salary range for this position based on experience and other factors (geographic location, etc.). Actual pay may vary. This job posting will remain open until the position is filled.

General Dynamics Mission Systems (GDMS) engineers a diverse portfolio of high technology solutions, products and services that enable customers to successfully execute missions across all domains of operation. With a global team of 12,000+ top professionals, we partner with the best in industry to expand the bounds of innovation in the defense and scientific arenas. Given the nature of our work and who we are, we value trust, honesty, alignment and transparency. We offer highly competitive benefits and pride ourselves in being a great place to work with a shared sense of purpose. You will also enjoy a flexible work environment where contributions are recognized and rewarded. If who we are and what we do resonates with you, we invite you to join our high-performance team!

Equal Opportunity Employer / Individuals with Disabilities / Protected Veterans